Closed loop control system having series connected coders

ABSTRACT

A control system for disposing each of a plurality of utilization circuits in a state responsive to the state of corresponding utilization controls. A plurality of series connected coders detect the state of the utilization controls associated therewith. Decoders associated with each of said coders and in series connection in the same sequence as said corresponding coders control the state of the corresponding utilization circuits. A column timer is in series connection with said coders and decoders for applying control signals thereto. Each of said coders and decoders are sequentially activated to a first active state during which they are operative to perform their assigned functions. Thereafter, each activated coder and decoder assumes an inactive state in which they permit the passage of control signals and data therethrough. Said control signals can be applied in either direction along said series connections.

United States Patent 72] Inventors Martin J. Slavin PrimaryExaminer-Harold l. Pitts Huntington; AttarneyBlum, Moscovitz, Friedman &Kaplan Kenneth Cohen, Smithtown; Morton Pullman, East Northport, all of,N.Y. [21] Appl. No. 855,527 [22] Filed Sept. 5, 1969 [45] Patented June15, 1971 [73] Asslgnee Inst-[Imam Systems Corporation ABSTRACT: Acontrol system for disposing each of a plurali- H'mtmgmn ty ofutilization circuits in a state responsive to the state of correspondingutilization controls. A plurality of series connected [54] CLOSED LOOPCONTROL SYSTEM HAVING coders detect the state of the utilizationcontrols associated SERIES CONNECTED CODERS therewith. Decodersassociated with each of said coders and in 15 Claims 4 Drawing Figsseries connection in the same sequence as said corresponding coderscontrol the state of the corresponding utilization cir- US. Cl. cuit Acolumn timer is in series connection said coders 340/147 and decodersfor applying control signals thereto. Each of said [51] Int. Cl H0419/00 coders and decoders are sequentially activated to a fi active of v63, tate during they are operative to perform their as- 147 signedfunctions. Thereafter, each activated coder and decoder assumes aninactive state in which the ermit the [56] References cued passage ofcontrol signals and data therethrough S id control UNITED STATES PATENTSsignals can be applied in either direction along said series con-3,075,l77 1/1963 Derr 340/163 nections.

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CW7? c0052 L1 c0052 60052 A 8005? ur/uzn- UI'IL/ZA- ur/uz4 ur/z/zar/o/v770M 710M 770 co/vrmas con/mats cam-045 (av/790 s J00. 5026 7396 JunPATENTEU JUN} 5 IENI SHEU 1 [1F 4 PATENTEU JUN1 5 |97l SHEET 2 UP 4CLOSED LOOP CONTROL SYSTEM HAVING SERIES CONNECTED CODERS BACKGROUND OFTHE INVENTION This invention relates generally to control systemsutilized ro permit the control from a plurality of discrete stations, ofa plurality of utilization circuits associated therewith. An example ofsuch a system would be the service system of an aircraft wherein theplurality of stations are the seat locations therein. Another example ofsuch a system would be a burglar and/or fire alarm system wherein theplurality of stations are the monitoring stations therein. Each seat orgroup of seats has a number of utilization circuits associated therewithsuch as service call lights and lamps for reading or generalillumination. In the art, it is customary to provide direct wiringbetween a utilization control, such as a switch at each seat, and thecorresponding utilization circuit. This approach results in largeamounts of cabling and therefore added expense and weight in theaircraft. Still further cabling and expense is added to the cost of asystem if centrally located supervisory utilization circuits, such as acentral attendant call light, responsive to the remotely locatedsupervisory control means are to be provided.

As an alternative to direct wiring between the individual utilizationcontrols and corresponding utilization circuits, a system utilizingmultiplexing techniques has been proposed wherein a coder is associatedwith each utilization control for transmitting data to a data line inassigned time slots representative of the state of said utilizationcontrol, and a decoder is provided associated with the correspondingutilization circuits for detecting in assigned time frames from saiddata line said state data and controlling said utilization circuits inresponse thereto. Said system, in addition to the data line, disposesthe coders and decoders, respectively, in series connection forsequential operation. Such a system suffers from the disadvantage thatif the data line or series connection breaks, the elements downstream ofthe break are rendered inoperative. Further, the provision of bothseries connections and a separate date line adds to the cabling andexpense of the system.

SUMMARY OF THE INVENTION Generally speaking, in accordance with theinvention, a closed-loop control system for placing said utilizationcircuits in a state responsive to the state of corresponding utilizationcontrol means is provided. Said system includes a plurality of seriesconnected coder means for detecting the state of the utilization controlmeans associated therewith and decoder means associated with each ofsaid coder means for controlling the state of the correspondingutilization circuits. The decoder means are in series connection in thesame sequence as the corresponding coder means. Column timer means isprovided in series connection with the plurality of coder means and theplurality of decoder means for applying control signals to said seriesconnections.

The coder and decoder means are sequentially activated in response tothe control signals during assigned time slots. Each coder, when firstactivated during a cycle of said system, assumes an activestate duringwhich it transmits in assigned time slots data representative of thestate of the utilization control means associated therewith to thecolumn timer means through any of the coder means previously activatedduring said cycle. Thereafter, for the balance of the cycle, the codermeans is in an inactive state during which it passes the control signaland the data transmitted by downstream coder means. The column timermeans is adapted to incorporate in the control signal applied to thedecoder means, the data representative of said utilization control meansstates. Each decoder means is adapted, when first activated during acycle of said system, to assume an active state wherein it receivesduring assigned time slots said data from said column timer meansthrough any previously activated decoder means to control thecorresponding utilization circuits. Thereafter, for the balance of saidcycle, each decoder means is placed in an inactive state wherein itpasses the control signal to downstream decoder means.

The control signal preferably includes clock timing and synchronizationportions. The coder and decoder means are adapted to be reset inresponse to said synchronization portion to commence a new cycle of thesystem. The sequential operation of the system is responsive to theclock timing components of said control signal.

The column timer is adapted to apply the control signal in one directionalong said series connections during some cycles of said system and inthe other direction during other cycles of said system, the coder anddecoder means being operative in response to control signals received ineither direction. The column timer means may be provided with loop errordetector means adapted to detect a characteristic portion of saidcontrol signals from the last activated of said series connected coderand decoder means and alarm means connected to said loop error detectormeans, said loop error detector means being adapted to activate saidalarm means upon the failure to detect said characteristic portion ofsaid control signals.

The system may include supervisory utilization control means whichproduce data representative of the state in which selected utilizationcircuits are to be placed, said column timer being adapted to apply suchdata in assigned time slots to the control signal applied to saiddecoder means in place of the corresponding data from said coder means.Said system may be adapted to permit a utilization control means to beresponsive to data from an appropriate supervisory utilization controlmeans, if desired.

Both the coder and decoder means are provided with appropriate gatingmeans responsive to gating and direction signals generated therein totransmit and utilize the control signals applied thereto in order toperform the abovedescribed functions.

Accordingly, it is an object of this invention to provide a close-loopcontrol system which permits individual control of a variety ofutilization circuits.

Another object of the invention is to provide a close-loop controlsystem wherein the elements on both sides of a break in said closed loopare operative despite said break.

A further object of the invention is to provide a closed-loop controlsystem adapted to detect breaks in said loops to activate an alarm inresponse thereto.

Still another object of the invention is to provide control elementsadapted for use in series connected arrangements incorporating aplurality of like elements, each of said elements being sequentiallyoperated for the transmission or receipt of data and thereafter,although inactive, permitting the passage of control signals and datatherethrough.

Still other objects and advantages of the invention will in part beobvious and will in part be apparent from the specification.

The invention accordingly comprises the features of construction,combinations of elements, and arrangement of parts which will beexemplified in the constructions hereinafter set forth, and the scope ofthe invention will be indicated in the claims.

BRIEF DESCRIPTION OF THE DRAWINGS For a fuller understanding of theinvention, reference is had to the following description taken inconnection with the accompanying drawings, in which:

FIG. 1 is a schematic representation of one type of closedloop controlsystem according to the invention;

FIG. 2 is a schematic representation of the column timer of the systemof FIG. 1;

FIG. 3 is a schematic representation of the coder of the system of FIG.I; and

FIG. 4 is a schematic representation of the decoder of the system ofFIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 1, theclosed-loop control system depicted incorporates a column timer having apair of coder terminals 12 and 14 and a pair of decoder terminals 16 and18. Connected in series with said coder terminals are a plurality ofcoders 20a, b, c, ...,n. Each coder is provided with a pair of terminals22 and 24 for said series connection, interconnected by coder line 26.Operatively connected to each coder 20, by means of lines 28, are one ormore utilization controls 28a, b, c, ,n. Each utilization control isadapted to be set in one or more states associated with the states inwhich the corresponding utilization circuits 32a, b, c, ,n are to beplaced. Each coder 20 is adapted to detect the states of itscorresponding utilization controls 30 and to store data representativeof said states.

Connected in series with decoder terminals 16 and 18 of column timer 10are a plurality of decoders 34a, b, c, ,n. Each decoder is provided witha pair of terminals 36 and 38 interconnected in said series connectionby decoder line 40. Each decoder 34 is connected, by means of lines 42to one or a group of utilization circuits 32. Said decoders are adaptedto place their corresponding utilization circuits in the desired statein response to data received thereby in assigned time slots.

Each coder 20 is associated with the decoder 34 connected to theutilization circuits 32 which are, in turn, associated with itsutilization controls 30. Thus, coder 20b is associated with utilizationcontrols 30b which are adapted to control utilization circuits 32b.Accordingly, decoder 34b is associated with coder 20!). Further, theassociated coders and decoders are disposed in their respective seriesconnection in the same sequence. In this manner, when said coders anddecoders are sequentially operated, only the corresponding pair of saidcoders and decoders are activated at any instant.

The closed-loop system according to the invention is adapted forcyclical operation. During each cycle, the column timer 10 applies acontrol signal to either of decoder terminals 12 and 14. Said controlsignal includes synchronization and clock timing components in assignedtime frames. Further, time frames within said signal are allotted toeach element of data which is to be transmitted during the operation ofthe system. Each cycle of the system is represented by a time framesubdivided into a plurality of said time slots. For example, time slotswould be allocated to contain data representative of the states of eachof the three utilization controls 30a and each of the two utilizationcontrols 30c. The clock timing components of said control signal canconsist, for example, of a series of spaced pulses. The synchronizationcomponent of said control signal may consist of a group of time slotsduring which no pulses are present, said synchronization component beingutilized to reset coders 20 and decoders 34 either at the end orbeginning of a cycle. Column timer 10 is also adapted to apply a controlsignal of similar construction to either of decoder terminals 16 and 18.

Assume that in one cycle, column timer 10 applies said control signal tocoder terminal 12, all of said coders 20 having been previously reset toa not-yet-activated state in response to the synchronization componentduring the previous cycle. Said control signal would be detected atterminal 22 of coder 20a to place said coder in an active state which ismaintained for a time period consisting of a predetermined number oftime slots. During said time period, coder 20a transmits back throughterminal 22 thereof, in appropriate time slots, the data representativeof the state of utilization controls 30a. At the end of said timeperiod, as determined by the detection of a predetermined number of saidclock timing components, coder 28 is placed in an inactive state duringwhich the data stored therein is no longer transmitted, but the controlsignal passed therethrough, out of terminal 24 and into terminal 22 ofcoder 20b. Coder 20b is then activated for a predetermined time periodand transmits the data representative of the state of utilizationcontrols 30b out of its terminal 22 in the direction of column timerterminal 12. Since coder 20a is in its inactive state, said data ispassed therethrough from its terminal 24 to its terminal 20. Thissequential operation continues until the nth coder has gone through anactive state, at which time a synchronization component of the controlsignal resets all of coders 20 to dispose said coders in thenot-yet-activated state for the next cycle. Each coder, when firstactivated, receives the control signal from the downstream coders andpasses the data back through said downstream coders to column timer 10.

In like manner, column timer 10 will apply a control signal to decoderterminal 16 which first activates decoder 340. When so activated, saiddecoder receives in assigned time frames, the data transmitted by coder200, said column timer having interposed said data in the control signalapplied to decoder terminal 16. In response to said data, decoder 34aplaces utilization circuits 32a in the desired state. After remainingactive for a time period corresponding to the active time period ofcoder 20a, decoder 34a assumes an inactive state and passes the controlsignal along decoder line 40 from its terminal 38 to the terminal 36 ofdecoder 34b. In the embodiment shown in the drawings, decoders 34 do notrequire the capability of transmitting data back to column timer 10, andneed only pass the control signal therethrough during their inactivestate,

All of the coders 20 are preferably identical and permitinterchangeability and ready maintenance. In like manner, all of thedecoders are preferably identical and interchangeable among themselves,the operation of the system being dependent on the placement of aparticular coder or decoder in the series connection, rather than thedesign of a particular one of said coders or decoders.

Column timer 10 is adapted to apply said control signal to coderterminal 12 during some cycles and to coder terminal 14 during othercycles and in like manner to apply said control signal to decoderterminal 16 during some cycles and to decoder terminal 18 during othercycles. When the control signals are applied to terminals 14 and 18respectively, the system operates in a like manner only the firstactivated of said coders and decoders are coder 20n and decoder 34n, theremaining coders and decoders being sequentially operated in the mannerdescribed above with the data from the respective coders beingtransmitted back to column timer coder terminal 14. The system isprovided with a supervisory control 44 connected to column timer 10through line 46. Said supervisory control is preferably centrallylocated and adapted to apply data to column timer 10 during appropriatetime slots to govern the state of certain of utilization circuits 32.The column timer is adapted to apply the data from supervisory control44, if present, in place of the corresponding data from the appropriatecoders 20 so that the state of the utilization circuits is determined bythe state of supervisory control 44. The system also includes asupervisory utilization circuit 48 connected to column timer 10 by line50, said column timer being adapted to actuate said supervisoryutilization circuit upon detecting certain data in assigned time slotsof said control signal.

In order to more particularly understand the operation of the system andfurther embodiments and features thereof, reference is now had to FIG. 2which shows a schematic representation of one embodiment of column timer10 according to the invention. The basic system timing for theclosed-loop control system according to the invention is obtained fromoscillator 60 which is operatively connected through line 62 to counter64. Said counter generates the basic timing pulses which govern theoperation of the system. Said timing pulses are applied through lines 66to basic timing decoding matrix 68 which produces, from the pulse outputof counter 64 the specific timing pulses required to control the variouselements of the system. Thus, coder timing signals are passed along line70 to coder clock/data logic 72 which assembles and structures thecontrol signal applied to the series connected coders 20. in likemanner, decoder timing signals are passed from decoding matrix 68through line 74 to decoder clock/data logic 76 which is adapted tostructure and assemble the control signal applied to the seriesconnected decoders 34, the latter control signal also incorporating thedata from coders 20.

Counter 64 also transmits a timing signal which determines the directionalong said series connected coders and decoders that said controlsignals are applied. For purposes of identification, coder terminal 14and decoder terminal 16 are designated the right terminals while coderterminal 12 and decoder terminal 18 are designated the left terminals Toeffect this determination, counter 64 applies left timing pulses alongline 78 and right timing pulses along line 80 to both decoder clock/datalogic 76 and coder clock/data logic 72. Said timing pulses arepreferably alternately applied along lines 78 and 80 so that the controlsignals are alternately applied to the respective coder and decoderterminals during consecutive cycles of the system. Thus, during onecycle, coder clock/data logic 72 would apply the control signal throughtransmitter 80 to coder terminal 14 and the seriesconnected coders 20.The data transmitted by said coders would be received back at coderterminal 14 and applied to receiver 82 which transmits said data signalalong line 84 to decoder clock/data logic 76 for incorporation in thecontrol signal thereof. In the next cycle, coder clock/data logic 72applies the control signal through transmitter 86 to coder terminal 12and the return data is received at receiver 88 and passed along line 90to decoder clock/data logic 76.

In like manner, said decoder clock/data logic alternately transmits itscontrol signal along transmitters 92 and 94 to decoder terminals 16 and18 respectively.

While the alternate application of control signals to the right and leftterminals is preferred, any combination of application of the controlsignals thereto may be utilized, so long as the control signal isapplied to the right" terminals during some cycles and to the left"terminals during other cycles.

In order to detect breaks in the series connections of said coders anddecoders, loop error detector 96 is provided. Said loop error detectoris connected through receivers 96, 98, 100 and 102 to decoder terminals16 and 18 and coder terminals 14 and 12 respectively. Said loop errordetector is adapted to detect the presence of the clock timing componentof the respective control signals at the coder and decoder terminalsconnected to the last coder and decoder in the series connection. Thus,if the control signal were applied to line 16 and there were no break inthe series-connected decoders, loop error detector 96 would detect theclock pulse through receiver 98 which taps off decoder terminal 18. Ifloop error detector 96 fails to detect such clock timing signals duringthe appropriate time slots, an activating signal is applied along line104 to supervisory utilization circuit 48 to activate an alarm meanssuch as a bell or light. Timing signals for said loop error detector arereceived along line 106 from basic timing decoding matrix 68 while theright" and left" timing signals are received from counter 64 along lines78 and 80.

If desired, loop error detector 96 can be adapted to limit theapplication of control signals to only left or right terminals, ifdesired due to the location of the break in the series connection. Forthis purpose, said loop error detector is connected to decoderclock/data logic 76 and coder clock/data logic 72 by lines 110 and 112which control the opening of the right and left loops respectively.

The supervisory control 44 may consist of a plurality of manuallyoperated test function switches 114 operatively connected to a testfunction logic 116 by lines 118 for the test of the system. Timing forsupervisory control 44 is obtained along line 120 from basic timingdecoding matrix 68. The output from test function logic 116 is takenalong 122 to decoder clock/data logic 76 to provide the supervisory datafor the control of the various utilization circuits 32, along line 124to loop error detector 96 and supervisory utilization circuit 48 to testthese components, and along line 126 to coder clockldata logic 72 toprovide data thereto for insertion in the appropriate time slots of thecontrol signal produced thereby. The latter data is utilized to resetcertain utilization controls 30.

Turning now to FIG. 3, one embodiment of a coder 20 according to theinvention is shown therein. As described above, the control signal caninitially be applied to either terminal 22 or terminal 24. Connected toterminal 22 are a pair of receivers 130 and 132 and a pair oftransmitters 134 and 136. in like manner, a pair of receivers 138 and140 and a pair of transmitters 142 and 144 are connected to terminal 24.The output of receiver 130, which contains the signal applied toterminal 22, is applied along line 146 to legitimatizing logic 148adapted to distinguish between the clock timing portions of the controlsignal and noise and other spurious signals and to pass along line 150to direction logic 152 the clock timing portion of said control signal.In like manner, receiver 138 passes along line 154 the control signal,when received, to legitimatizing logic 156, which in turn, passes theclock timing component of a signal from terminal 24 to direction logic152 along line 158. Said directional logic is adapted to produce agating signal along lines and 162 representative, respectively, ofwhether the control terminal was first applied at terminal 22 orterminal 24.

Each coder 20 is provided with an internal counter 164 for providinginternal timing for said coder. The clock timing portions of the controlsignals applied to the coder are passed from direction logic 152 tocounter 164 along line 166 for the sequential operation thereof. Theoutput of counter 164 consists of gating signals representative of theactive and inactive states of the coder which are passed respectivelyalong lines 168 and 170. When the clock signal is first received, theactive period is commenced and the signal is passed along line 168.After the allotted time period during which the coder performs itsassigned task is completed, the signal is passed along line 170 tosignify the inactive state. A further output from counter 164 is alonglines 172 to decoding matrix 174 which produces the operative timingsignals for the operation of the system, and which also receives theapplied clock timing signals from direction logic 152 along line 166.

One output of decoding matrix 174 is along line 176 to data bit timelogic 178 which produces gating signals in the time slots assigned forthe transmission of data. Thus, gating signals are transmitted alongline 180 during the time slots assigned to the transmission of data bythe coder while gating signals are applied along line 182 during thetime slots assigned to the transmission of data by the column timer 10for the purposes of resetting certain utilization controls 30.

Utilization control circuits 30 are connected along lines 28 to datastorage and shift register 184 adapted to detect the state of saidutilization control circuits and store data representative of saidstates. Further, said data storage and shift register is adapted totransmit, in appropriate time slots, said data. Data storage and shiftregister 184 receives timing signals from deciding matrix 174 along line186 and receives the clock timing components of the control signal fromdirection logic 152 along line 166. Data is transmitted out of said datastorage and shift register along line 188. Certain data, namely the datafrom the column timer is received by said data storage and shiftregister from line 190. In this connection, receiver 132 connected toterminal 22 receives the signal applied thereto and passes it throughline 192 to legitimatizing logic 194. Said legitimatizing logic isadapted to distinguish between data components of the received signaland noise and other spurious signals and to transmit said datacomponents along line 194 to OR gate 198. In like manner, receiver 140receives the signal from terminal 24 and applies said signal throughline 200 to legitimatizing logic 202 which applies the data componentsthereof along line 204 to OR gate 198. The output of said OR gate ispassed along line to data storage and shift register 184.

In order to detect the synchronization portion of the control signal,synchronization detector 206 taps off lines 166 and 190, by means oflines 208 and 210 respectively for the purposes of detecting thepresence of signals on these lines. In the embodiment shown in thedrawings, the absence of a signal for a predetermined period of timewould indicate synchronization and result in the transmission of a resetsignal along line 212 from sync detector 206 to direction logic 152,data storage and shift register 184 and counter 164.

The operation of the coder is governed by a group of gates connected tothe transmitters which determine the routing of the various data andcontrol signals in response to the abovementioned gating signals.Specifically, AND gate 220 is connected to transmitter 134 and adaptedto transmit the clock signal received from terminal 24 as applied alongline 222, which taps line 154, when the coder is in the inactive state.The control signal may be received from terminal 22, and a like AND gate224 is connected to transmitter 142. AND gate 224 transmits the clocktiming component of the control signal received from terminal 22 alongline 226, which taps line 192. AND gates 220 and 224 are gated intooperation by the direction gating signals from direction logic 152 andthe state gating signals from counter 164.

Transmitter 136 is driven by OR gate 228 which is activated by any oneof AND gates 230, 232 and 234. AND gate 230 derives the signal that ittransmits through transmitter 136 to terminal 122 from line 236 whichtaps off line 200, and therefore receives the signal from terminal 24.Said AND gate is gated open to transmit the signal received along line236 when the control signal was first received at terminal 24 asdetermined in direction logic 152, during the inactive state asdetermined at counter 164, and during the time slots assigned for thetransmission of column timer data as determined at data bit time logic178. Accordingly, AND gate 230 is adapted to specifically transmitcolumn timer data through the coder from terminal 24 to terminal 22 whensaid coder is in the inactive or passive state.

AND gate 232 is adapted to transmit to terminal 22 the data from datastorage and shift register 184 received along line 188 when the controlsignal was originally applied to terminal 22 as determined by directionlogic 152 and during the active state of the counter as determined bycounter 164. This constitutes the only transmission during the activestate. The data is transmitted to the column timer through thepreviously activated coders.

AND gate 234 transmits to terminal 22 date received from terminal 24along line 236, which taps line 200. This AND gate is adapted totransmit data from terminal 24 to terminal 22 when the coder is in theinactive state as determined by counter 164, the control signal wasoriginally applied to terminal 24 as determined by direction logic 152and during time slots assigned to the transmission of coder data asdetermined by data bit time logic 178. ln effect, AND gate 234 is usedto transmit through the coder, all state data transmitted by othercoders while in their active states.

The gating system of coder is symmetrical to permit operation fromeither of terminals 22 and 24. Accordingly, OR gate 238 connected totransmitter 144 for applying a signal to terminal 24 corresponds to ORgate 228 and has connected thereto-three AND gates 240, 242 and 244. ANDgate 240 corresponds to AND gate 230 and transmits the column timer datareceived along line 246 which taps the line 192 to receive the dataportion of the signal from terminal 22. AND gate 240 differs from ANDgate 230 in that it is operative only when the control signal is firstapplied to terminal 22.

AND gate 242 corresponds to AND gate 232 and transmits, during theactive state of the coder, the data transmitted by data storage andshift register 184, if the original control signal was received fromterminal 24. Finally, AND gate 244 is similar to AND gate 234 andtransmits, in a like manner, the coder data received from terminal 22along line 246.

Reference is now had to FIG. 4 which shows a detailed block diagram of adecoder 34 according to the invention. Said decoder operates on asimilar principal as coder 20, but because it is required to performfewer tasks, is of simpler construction. Specifically, receiver 260 andtransmitter 262 are connected to terminal 36 while receiver 264 andtransmitter 266 are connected to terminal 38. The output of receiver260, which would consist of the control signal applied from column timer10, is applied through line 268 to legitimatizing logic 270 which isadapted to differentiate between data and clock portions of said signalas well as to detect and reject noise and other spurious signals. Theclock portion of said control signal is applied along line 272 todirection logic 274 which is of similar construction to direction logic152 of coder 20. In like manner, the control signal from terminal 38 isapplied through receiver 264 and line 276 to legitimatizing logic 278,which in turn applies through line 280 the clock timing portion of saidsignal to direction logic 274. Said direction logic produces gatingsignals along lines 282 and 284 representative of the receipt of saidcontrol signal at terminals 36 and 38 respectively. Decoder 34 isprovided with a counter 286 which receives the clock signal fromdirection logic 274 for internal timing of the decoder. Said counter isconnected along lines 288 to decoding matrix 290. Said decoding matrixproduces and transmits along lines 292 to data storage registers anddrivers 294 the timing signals necessary for the sequential operation ofsaid data storage registers and drivers. Said data storage registers anddrivers are connected along lines 42 to utilization circuits 32 and areadapted to dispose said utilization circuits in the states indicated bythe data stored therein. Counter 286 is adapted to produce gatingsignals representative of the periods during which said decoder is to bedisposed in the inactive and active states. The initial active stateperiod is represented by a gating signal along lines 298 to data storageregisters and drivers 294 to place same in operative condition for thecontrol of its associated utilization circuits. The inactive stategating signal is applied along line 296. The data component of thesignal passed by legitimatizing logic 270 is transmitted along line 300to OR gate 302. In like manner, the data component of the signalreceived from terminal 38 is passed by legitimatizing logic 278 alongline 304 to OR gate 302. Said OR gate passes said data signal along line306 to data storage registers and drivers for storage and operationthereby when activated by a gating signal along line 298.

Decoder 10 is provided with a synchronization detector 308 which tapsthe clock and data outputs of direction logic 274 and OR gate 302 bymeans of lines 310 and 312 respectively. Upon detecting thesynchronization component of the control signal, preferably by theabsence of any data or clock signals for a predetermined period, asynchronization signal is passed by synchronization detector 308 alongline 314 to data storage registers and drivers 294 and counter 286. Inthis manner, the decoder is reset for the next cycle.

Decoder 10 is required to transmit signals therethrough only whendisposed in the inactive state, in which case it passes the controlsignals from the column timer to the decoder in the active state. ANDgate 316 is adapted to transmit to terminal 36 through transmitter 262the signal received from terminal 38. For this purpose, line 318 tapsline 276 and transmits the signal from terminal 38 to AND gate 316. SaidAND gate is adapted to pass a signal only when said decoder is in aninactive stage as determined by counter 286 and the control signal wasfirst received at terminal 38 as determined by direction logic 274. inlike manner, AND gate 320 will pass the control signal from terminal 36through transmitter 266 to terminal 38 when the decoder is in theinactive state and the control signal was first applied to terminal 36.The signal is applied to AND gate 320 through line 322 which taps line268.

The specific construction of the coders and decoders permits theclosed-loop control system to operate in both directions along said loopso that, in the event of a break in said loop, coders and decoders onboth sides of said loop would remain operative. Further, thisconstruction permits the coders to be identical among themselves sincethe timing and sequential operation of the system is dependent, not onthe unique characteristic of each coder, but on the position of thecoder in the series connection. The same is true for the decoders whichmay be interchangeable among themselves.

This arrangement offers substantial advantages both in terms of ease ofmaintenance, and total cost for the system.

The coder and decoder devices according to the invention are not limitedin their application to the system according to the invention, butrather, may be utilized as control elements where each of a group ofseries connected elements are to be sequentially activated for thepurposes of receiving or transmitting data.

It will thus be seen that the objects set forth above, among those madeapparent from the preceding description, are efficiently attained and,since certain changes may be made in the above constructions withoutdeparting from the spirit and scope of the invention, it is intendedthat all matter contained in the above description or shown in theaccompanying drawings shall be interpreted as illustrative and not in alimiting sense.

What we claim is:

l. A closed-loop control system for a plurality of discrete stationscomprising a plurality of utilization circuits; at least one utilizationcontrol means disposed at each of said stations and associated with atleast one of said utilization circuits; a plurality of series connectedcoder means for detecting the state of the utilization control meansassociated therewith; decoder means associated with each of said codermeans for controlling the state of the corresponding utilizationcircuits, said decoder means being in series connection in the samesequence as said corresponding coder means; column timer means in seriesconnection with said plurality of coder means and said plurality ofdecoder means for applying control signals to said series connections,said coder and decoder means being sequentially activated in response tosaid control signals during assigned time slots, each of said codermeans being adapted, when first activated during a cycle of said system,to transmit in assigned time slots data representative of the state ofthe utilization control means associated therewith to said column timermeans through any of said coder means previously activated during saidcycle, said coder means being adapted to thereafter for the balance ofsaid cycle to pass the control signal and the data transmitted bydownstream coder means; said column timer means being adapted toincorporate in the control signal applied to said decoder means the datarepresentative of said utilization control means states; each of saiddecoder means being adapted, when first activated during a cycle of saidsystem, to receive during assigned time slots said data from said columntimer means through any previously activated decoder means to controlthe corresponding utilization circuits, said decoder means being adaptedto thereafter for the balance of said cycle pass the control signal todownstream decoders, whereby each of said utilization circuits is placedin a state responsive to the state of its corresponding utilizationcontrol means.

2. A closed-loop control system as recited in claim 1, wherein saidcolumn timer means is adapted to produce control signals incorporating asynchronization portion in each cycle of said system, said coder anddecoder means being adapted to be reset in response to saidsynchronization portion to commence a new cycle of said system.

3. A closed-loop control system as recited in claim 1, wherein saidcolumn timer means includes a pair of coder and a pair of decoderterminals for series connection, respectively, with said coder anddecoder means, said column timer means being adapted to apply saidcontrol signal to one of said coder terminals and one of said decoderterminals during some cycles of said system and to the other ofsaidcoder terminals and the other of said decoder terminals during othercycles of said system, said coder and decoder means being operative inresponse to control signals received in either direction along saidrespective series connections.

4. A closed-loop control system as recited in claim 3, wherein saidcolumn timer means includes loop error detector means connected to saidcolumn timer coder and decoder terminals adapted to detect acharacteristic portion of said control signals from the last activatedof said series connected coder and decoder means; and alarm meansconnected to said loop error detector means, said loop error detectormeans being adapted to activate said alarm means upon the failure todetect said characteristic portion of said control signals.

5. A closed-loop control system as recited in claim 1, wherein saidcolumn timer means is adapted to produce control signals including clocktiming components in assigned time slots, the sequential operation ofsaid system being responsive to said clock timing components.

6. A closed-loop control system as recited in claim 1, wherein saidcoder means are substantially identical, and said decoder means aresubstantially identical.

7. A closed-loop control system as recited in claim 1, includingsupervisory utilization control means connected to said column timermeans and associated with at least one of said utilization circuits,said column timer means being adapted to detect the state of saidsupervisory utilization control means and to incorporate in the timeslots of the control signal applied to said decoder means datarepresentative of said supervisory utilization control means states forthe control of said utilization circuits by the corresponding decodermeans, said data being applied in place of the data transmitted by thecoder means associated with said utilization circuits.

8. A closed-loop control system as recited in claim 1, wherein saidcoder means are adapted to establish the state of at least oneutilization control means associated therewith, said system includingsupervisory utilization control means associated with said controllableutilization control means, said column timer means being adapted todetect the state of said supervisory utilization control means and toincorporate in assigned time slots of the control signal applied to saidseries connected coder means data representative of the state of saidsupervisory utilization control means, each of said coder means beingadapted to receive such data when first activated for controlling thestate of said controllable utilization control means.

9. A closed-loop control system as recited in claim 3, wherein saidcolumn timer means is adapted to produce a control signal forapplication to said series connected coder means includingsynchronization and clock timing components, the sequential operation ofsaid coder means between a first not-yet-activated state, a secondactive state and a third inactive state being in response to said clocktiming components during each cycle of said system, said coder meansbeing adapted to be reset to said not-yet-activated state in response tosaid synchronization component.

10. A closed-loop control system as recited in claim 9, wherein saidcoder means includes a pair of terminals for said series connection;direction logic means connected to said terminals, for producing adirection signal representative of the terminal from which said controlsignal is received; data storage means for storing data representativeof the state of the corresponding utilization control means; gate signalmeans for generating, in response to said clock timing components ofsaid control signal applied thereto during said active and inactivestates of said coder means, gating signals representative respectivelyof said inactive state, active state, and the time slots assigned to thetransmission of data; and gating means responsive to said gating anddirection signals, said gating means being connected to the terminal atwhich said control signal is received to apply to said terminal, duringsaid active state, the data stored in said data storage means and,during the time slots assigned to the transmission of data occurringduring said inactive state, the data received from the other of saidterminals, said gating means being connected to the other of saidterminals, for the application thereto, during said inactive state, ofthe clock timing components of said control signal.

11. A closed-loop control system as recited in claim 10, wherein saidcontrol signal includes data transmitted by said column timer means inassigned time slots, said data storage means being connected to saidterminals to receive such data during assigned time frames, said gatingsignal means producing gating signals representative of the time slotsassigned to said data transmitted by said column timer, said gatingmeans, during said time slots assigned to said column timer dataoccurring during said inactive state, applying said column timer data tosaid other terminal,

12. A closed-loop control system as recited in claim 9, wherein saiddecoder means includes a pair of terminals for said series connection;direction logic means connected to said terminals for producing adirection signal representative of the terminal to which said controlsignal is applied; data storage means connected to said terminals fordetecting data components of said control signal during assigned timeslots; gating signal means for producing gating signals representativeof said active and inactive states respectively in response to the clocktiming components of said control signal; and gating means responsive tosaid direction and gating signals for applying, during said inactivestate, said control signal to the terminal to which said control signalwas not applied.

13. A control element for series connection with a plurality of likeelements in a closed loop, said closed loop having, at one point in saidloop, a control signal applied in either direction along said loop forthe sequential transmission during assigned time slots of operative databy said control elements, said control element comprising a pair ofterminals for said series connection; direction logic means connected tosaid terminals for producing a direction signal representative of theterminal from which said control signal is received; data storage meansfor storing operative data; said control signal includingsynchronization and clock timing components, the sequential operation ofsaid control element between a first not-yet-activated state, a secondactive state and a third inactive state being in response to said clocktiming components during each cycle of said loop, said control elementbeing adapted to be reset to said not-yet-activated state in response tosaid synchronization component, gate signal means for generating, inresponse to said clock timing components of said control signal appliedthereto during said active and inactive states of said control element,gating signals representative respectively of said inactive state,active state, and the time slots assigned to the transmission of saidoperative data; and gating means responsive to said gating and directionsignals, said gating means being connected to the terminal at which saidcontrol signal is received to apply to said terminal, during said activestate, the operative data stored in said data storage means and, duringthe time slotsassigned to the transmission of such data occurring duringsaid inactive state, the data received from the other of said terminals,said gating means being connected to the other of said terminals, forthe application thereto, during said inactive state, of the clock timingcomponents of said control signal.

14. A control element as recited in claim 13, wherein said controlsignal includes operative data in assigned time slots, said data storagemeans being connected to said terminals to receive such control signaloperative data during assigned time frames, said gating signal meansproducing gating signals representative of the time slots assigned tosaid control signal operative data, said gating means, during said timeslots assigned to said control signal operative data occurring duringsaid inactive state, applying said control signal operative data to saidother terminal.

15 A control element for series connection with a plurality of likeelements in a closed loop, said closed loop having at one point in saidloop a control signal applied in either direction along said loop forthe sequential receipt during assigned time slots of operative data insaid control signal by said control elements, said control elementcomprising a pair of terminals for said series connection; directionlogic means connected to said terminals for producing a direction signalrepresentative of the terminal to which said control signal is applied;data storage means connected to said terminals for receiving operativedata components of said control signal during assigned time slots; saidcontrol signal means includin synchronization and clock timingcomponents, the sequentia operation of said control element between afirst not-yet-activated state, a second active state and a thirdinactive state being in response to said clock timing components duringeach cycle of said loop, said control element being adapted to be resetto said not-yet-activated state in response to said synchronizationcomponent, gating signal means for producing gating signalsrepresentative of said active and inactive states respectively inresponse to the clock timing components of said control signal; andgating means responsive to said direction and gating signals forapplying, during said inactive state, said control signal to theterminal to which said control signal was not applied.

1. A closed-loop control system for a plurality of discrete stationscomprising a plurality of utilization circuits; at least one utilizationcontrol means disposed at each of said stations and associated with atleast one of said utilization circuits; a plurality of series connectedcoder means for detecting the state of the utilization control meansassociated therewith; decoder means associated with each of said codermeans for controlling the state of the corresponding utilizationcircuits, said decoder means being in series connection in the samesequence as said corresponding coder means; column timer means in seriesconnection with said plurality of coder means and said plurality ofdecoder means for applying control signals to said series connections,said coder and decoder means being sequentially activated in response tosaid control signals during assigned time slots, each of said codermeans being adapted, when first activated during a cycle of said system,to transmit in assigned time slots data representative of the state ofthe utilization control means associated therewith to said column timermeans through any of said coder means previously activated during saidcycle, said coder means being adapted to thereafter for the balance ofsaid cycle to pass the control signal and the data transmitted bydownstream coder means; said column timer means being adapted toincorporate in the control signal applied to said decoder means the datarepresentative of said utilization control means states; each of saiddecoder means being adapted, when first activated during a cycle of saidsystem, to receive during assigned time slots said data from said columntimer means through any previously activated decoder means to controlthe corresponding utilization circuits, said decoder means being adaptedto thereafter for the balance of said cycle pass the control signal todownstream decoders, whereby each of said utilization circuits is placedin a state responsive to the state of its corresponding utilizationcontrol means.
 2. A closed-loop control system as recited in claim 1,wherein said column timer means is adapted to produce control signalsincorporating a synchronization portion in each cycle of said system,said coder and decoder means being adapted to be reset in response tosaid synchronization portion to commence a new cycle of said system. 3.A closed-loop control system as recited in claim 1, wherein said columntimer means includes a pair of coder and a pair of decoder terminals forseries connection, respectively, with said coder and decoder means, saidcolumn timer means being adapted to apply said control signal to one ofsaid coder terminals and one of said decoder terminals during somecycles of said system and to the other of said coder terminals and theother of said decoder terminals during other cycles of said system, saidcoder and decoder means being operative in response to control signalsreceived in either direction along said respective series connections.4. A closed-loop control system as recited in claim 3, wherein saidcolumn timer means includes loop error detector means connected to saidcolumn timer coder and decoder terminals adapted to detect acharacteristic portion of said control signals from the last activatedof said series connected coder and decoder means; and alarm meansconnected to said loop error detector means, said loop error detectormeans being adapted to activate said alarm means Upon the failure todetect said characteristic portion of said control signals.
 5. Aclosed-loop control system as recited in claim 1, wherein said columntimer means is adapted to produce control signals including clock timingcomponents in assigned time slots, the sequential operation of saidsystem being responsive to said clock timing components.
 6. Aclosed-loop control system as recited in claim 1, wherein said codermeans are substantially identical, and said decoder means aresubstantially identical.
 7. A closed-loop control system as recited inclaim 1, including supervisory utilization control means connected tosaid column timer means and associated with at least one of saidutilization circuits, said column timer means being adapted to detectthe state of said supervisory utilization control means and toincorporate in the time slots of the control signal applied to saiddecoder means data representative of said supervisory utilizationcontrol means states for the control of said utilization circuits by thecorresponding decoder means, said data being applied in place of thedata transmitted by the coder means associated with said utilizationcircuits.
 8. A closed-loop control system as recited in claim 1, whereinsaid coder means are adapted to establish the state of at least oneutilization control means associated therewith, said system includingsupervisory utilization control means associated with said controllableutilization control means, said column timer means being adapted todetect the state of said supervisory utilization control means and toincorporate in assigned time slots of the control signal applied to saidseries connected coder means data representative of the state of saidsupervisory utilization control means, each of said coder means beingadapted to receive such data when first activated for controlling thestate of said controllable utilization control means.
 9. A closed-loopcontrol system as recited in claim 3, wherein said column timer means isadapted to produce a control signal for application to said seriesconnected coder means including synchronization and clock timingcomponents, the sequential operation of said coder means between a firstnot-yet-activated state, a second active state and a third inactivestate being in response to said clock timing components during eachcycle of said system, said coder means being adapted to be reset to saidnot-yet-activated state in response to said synchronization component.10. A closed-loop control system as recited in claim 9, wherein saidcoder means includes a pair of terminals for said series connection;direction logic means connected to said terminals for producing adirection signal representative of the terminal from which said controlsignal is received; data storage means for storing data representativeof the state of the corresponding utilization control means; gate signalmeans for generating, in response to said clock timing components ofsaid control signal applied thereto during said active and inactivestates of said coder means, gating signals representative respectivelyof said inactive state, active state, and the time slots assigned to thetransmission of data; and gating means responsive to said gating anddirection signals, said gating means being connected to the terminal atwhich said control signal is received to apply to said terminal, duringsaid active state, the data stored in said data storage means and,during the time slots assigned to the transmission of data occurringduring said inactive state, the data received from the other of saidterminals, said gating means being connected to the other of saidterminals, for the application thereto, during said inactive state, ofthe clock timing components of said control signal.
 11. A closed-loopcontrol system as recited in claim 10, wherein said control signalincludes data transmitted by said column timer means in assigned timeslots, said data storage means being connected to said terminals Toreceive such data during assigned time frames, said gating signal meansproducing gating signals representative of the time slots assigned tosaid data transmitted by said column timer, said gating means, duringsaid time slots assigned to said column timer data occurring during saidinactive state, applying said column timer data to said other terminal.12. A closed-loop control system as recited in claim 9, wherein saiddecoder means includes a pair of terminals for said series connection;direction logic means connected to said terminals for producing adirection signal representative of the terminal to which said controlsignal is applied; data storage means connected to said terminals fordetecting data components of said control signal during assigned timeslots; gating signal means for producing gating signals representativeof said active and inactive states respectively in response to the clocktiming components of said control signal; and gating means responsive tosaid direction and gating signals for applying, during said inactivestate, said control signal to the terminal to which said control signalwas not applied.
 13. A control element for series connection with aplurality of like elements in a closed loop, said closed loop having, atone point in said loop, a control signal applied in either directionalong said loop for the sequential transmission during assigned timeslots of operative data by said control elements, said control elementcomprising a pair of terminals for said series connection; directionlogic means connected to said terminals for producing a direction signalrepresentative of the terminal from which said control signal isreceived; data storage means for storing operative data; said controlsignal including synchronization and clock timing components, thesequential operation of said control element between a firstnot-yet-activated state, a second active state and a third inactivestate being in response to said clock timing components during eachcycle of said loop, said control element being adapted to be reset tosaid not-yet-activated state in response to said synchronizationcomponent, gate signal means for generating, in response to said clocktiming components of said control signal applied thereto during saidactive and inactive states of said control element, gating signalsrepresentative respectively of said inactive state, active state, andthe time slots assigned to the transmission of said operative data; andgating means responsive to said gating and direction signals, saidgating means being connected to the terminal at which said controlsignal is received to apply to said terminal, during said active state,the operative data stored in said data storage means and, during thetime slots assigned to the transmission of such data occurring duringsaid inactive state, the data received from the other of said terminals,said gating means being connected to the other of said terminals, forthe application thereto, during said inactive state, of the clock timingcomponents of said control signal.
 14. A control element as recited inclaim 13, wherein said control signal includes operative data inassigned time slots, said data storage means being connected to saidterminals to receive such control signal operative data during assignedtime frames, said gating signal means producing gating signalsrepresentative of the time slots assigned to said control signaloperative data, said gating means, during said time slots assigned tosaid control signal operative data occurring during said inactive state,applying said control signal operative data to said other terminal. 15.A control element for series connection with a plurality of likeelements in a closed loop, said closed loop having at one point in saidloop a control signal applied in either direction along said loop forthe sequential receipt during assigned time slots of operative data insaid control signal by said control elements, said control elementcomPrising a pair of terminals for said series connection; directionlogic means connected to said terminals for producing a direction signalrepresentative of the terminal to which said control signal is applied;data storage means connected to said terminals for receiving operativedata components of said control signal during assigned time slots; saidcontrol signal means including synchronization and clock timingcomponents, the sequential operation of said control element between afirst not-yet-activated state, a second active state and a thirdinactive state being in response to said clock timing components duringeach cycle of said loop, said control element being adapted to be resetto said not-yet-activated state in response to said synchronizationcomponent, gating signal means for producing gating signalsrepresentative of said active and inactive states respectively inresponse to the clock timing components of said control signal; andgating means responsive to said direction and gating signals forapplying, during said inactive state, said control signal to theterminal to which said control signal was not applied.